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Hotspots Flops and uOps (Presented by Intel)


Multicore programming and task decomposition techniques to utilize ever increasing core counts on modern processors are generally well understood. However, single core optimizations are harder to comprehend. Understanding out-of-order execution of instructions as well as fully utilizing wide SIMD is critical to obtain the most performance on modern CPUs.

In this session, we focus on instruction and SIMD level parallelism techniques using Intel's Sandy Bridge micro-architecture as an example. We explain how instructions, including the new Advanced Vector Extensions (AVX), are decoded and executed out-of-order on the x86 back-end. We present sample workflows to identify bottlenecks in existing code, including architecture specific, and validate changes to obtain optimal code performance.

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  • GDC Europe 2011
  • Levent Akyil
  • Intel
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